1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to an improvement of an isolating portion, formed between a digital circuit region and an analog circuit region of a semiconductor integrated circuit, for preventing adverse effect such as an electrostatic surge or electrical noise.
2. Description of the Related Art
Conventionally, it is known that, in a semiconductor device including a digital circuit region and an analog circuit region, an isolating portion is formed between these regions to cut off an electrical noise, so that an electrical noise generated in the digital circuit region may not adversely affect the analog circuit region.
For example, Jpn. Pat. Appln. KOKOKU Publication No. 62-58668 entitled "C-NOS Integrated Circuit and Method of Using the Same" discloses a C-NOS (complementary insulating gate type) integrated circuit having a digital circuit region 51 and an analog circuit region 52 formed on an N type semiconductor substrate 50, as shown in FIG. 1. In this circuit, an isolating portion 56, including a P type well 53, a P.sup.+ type diffusion layer 54 formed on the P type well 53, and an electrode 55 in contact with the P.sup.+ type diffusion layer 54, is formed between the digital and analog circuit regions. The lowest potential of the used potentials is applied to the electrode 55, thereby shutting off both circuit regions from an electrical noise.
In the digital and analog circuit regions 51 and 52, a reference numeral 61 denotes a P type well, 62 an N.sup.+ type diffusion layer, 63 a P.sup.+ type diffusion layer, 64 a gate oxide film formed on a substrate surface, 65 an electrode in contact with the N.sup.+ type diffusion layer 62 or the P.sup.+ type diffusion layer 63, and 66 a gate 10 electrode for use in a MOS transistor formed on the gate oxide film 64.
FIG. 2 shows another example of a conventional isolating portion of an integrated circuit. In this circuit, a digital circuit region 51 and an analog circuit region 52 are individually surrounded by P type wells 67. P.sup.+ type diffusion layers 68 are respectively formed on the P type wells 67 and electrodes (not shown) are formed in contact with the P.sup.+ type diffusion layers 68. That portion of a semiconductor substrate 50 interposed between the circuit regions 51 and 52 forms an isolating portion 56. With this constitution, both circuit regions are shut off from an electrical noise.
Assume that an electrostatic surge input to a power source terminal (not shown) from an external device is input either the digital circuit region 51 or the analog circuit region 52 through a power source line (not shown). The electrostatic surge flows through the substrate 50. Since the conventional isolating portion 56 does not shut off the digital and analog circuit regions from an electrostatic surge, it cannot protect the circuit regions from electrostatic breakdown.
As described above, in the semiconductor device having the digital circuit region and the analog circuit region, the conventional isolating portion formed between the two circuit regions is disadvantageous in that it cannot shut off an electrostatic surge input from an external device to the power source terminal and cannot protect the circuit regions from electrostatic breakdown.